TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

Keunwoo Kim; Jente B. Kuang; Fadi H. Gebara; Hung C. Ngo; Ching-Te Chuang; Kevin J. Nowka

doi:10.1109/TED.2009.2030657

TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

Keunwoo Kim, Jente B. Kuang, Fadi H. Gebara, Hung C. Ngo, Ching-Te Chuang, Kevin J. Nowka

Department of Electronics Engineering

Research output: Contribution to journal › Article

6 Scopus citations

Abstract

This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.

Original language	English
Pages (from-to)	3033-3040
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	56
Issue number	12
DOIs	https://doi.org/10.1109/TED.2009.2030657
State	Published - Dec 2009

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Kim, K., Kuang, J. B., Gebara, F. H., Ngo, H. C., Chuang, C-T., & Nowka, K. J. (2009). TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability. IEEE Transactions on Electron Devices, 56(12), 3033-3040. https://doi.org/10.1109/TED.2009.2030657

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title = "TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability",

abstract = "This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.",

author = "Keunwoo Kim and Kuang, {Jente B.} and Gebara, {Fadi H.} and Ngo, {Hung C.} and Ching-Te Chuang and Nowka, {Kevin J.}",

year = "2009",

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doi = "10.1109/TED.2009.2030657",

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AU - Kuang, Jente B.

AU - Gebara, Fadi H.

AU - Ngo, Hung C.

AU - Chuang, Ching-Te

AU - Nowka, Kevin J.

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AB - This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.

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DO - 10.1109/TED.2009.2030657

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

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