Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

S. C. Song; M. Abu-Rahma; B. M. Han; L. Ge; S. S. Yoon; J. Wang; W. Yang; D. Liu; Chen-Ming Hu; G. Yeap

doi:10.1109/ICICDT.2009.5166287

Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

S. C. Song, M. Abu-Rahma, B. M. Han, L. Ge, S. S. Yoon, J. Wang, W. Yang, D. Liu, Chen-Ming Hu, G. Yeap

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V _ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1μm² below 32nm node.

Original language	English
Title of host publication	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages	165-168
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2009.5166287
State	Published - 1 Dec 2009
Event	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States Duration: 18 May 2009 → 20 May 2009

Publication series

Name	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Country	United States
City	Austin, TX
Period	18/05/09 → 20/05/09

Keywords

22nm
32nm
Bitcell
FinFet
Icell
MuGFET
SNM
SRAM
Vccmin

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Song, S. C., Abu-Rahma, M., Han, B. M., Ge, L., Yoon, S. S., Wang, J., Yang, W., Liu, D., Hu, C-M., & Yeap, G. (2009). Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 165-168). [5166287] (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166287

Song, S. C. ; Abu-Rahma, M. ; Han, B. M. ; Ge, L. ; Yoon, S. S. ; Wang, J. ; Yang, W. ; Liu, D. ; Hu, Chen-Ming ; Yeap, G. / Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. pp. 165-168 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

@inproceedings{9d01902b1d784411a40fefc3216f16d0,

title = "Systematic approach of FinFET based SRAM bitcell design for 32nm node and below",

abstract = "Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1μm2 below 32nm node.",

keywords = "22nm, 32nm, Bitcell, FinFet, Icell, MuGFET, SNM, SRAM, Vccmin",

author = "Song, {S. C.} and M. Abu-Rahma and Han, {B. M.} and L. Ge and Yoon, {S. S.} and J. Wang and W. Yang and D. Liu and Chen-Ming Hu and G. Yeap",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ICICDT.2009.5166287",

language = "English",

isbn = "9781424429332",

series = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

pages = "165--168",

booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

note = "null ; Conference date: 18-05-2009 Through 20-05-2009",

}

Song, SC, Abu-Rahma, M, Han, BM, Ge, L, Yoon, SS, Wang, J, Yang, W, Liu, D, Hu, C-M & Yeap, G 2009, Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. in 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009., 5166287, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp. 165-168, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, Austin, TX, United States, 18/05/09. https://doi.org/10.1109/ICICDT.2009.5166287

Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. / Song, S. C.; Abu-Rahma, M.; Han, B. M.; Ge, L.; Yoon, S. S.; Wang, J.; Yang, W.; Liu, D.; Hu, Chen-Ming; Yeap, G.

2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 165-168 5166287 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

AU - Song, S. C.

AU - Abu-Rahma, M.

AU - Han, B. M.

AU - Ge, L.

AU - Yoon, S. S.

AU - Wang, J.

AU - Yang, W.

AU - Liu, D.

AU - Hu, Chen-Ming

AU - Yeap, G.

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1μm2 below 32nm node.

AB - Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1μm2 below 32nm node.

KW - 22nm

KW - 32nm

KW - Bitcell

KW - FinFet

KW - Icell

KW - MuGFET

KW - SNM

KW - SRAM

KW - Vccmin

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U2 - 10.1109/ICICDT.2009.5166287

DO - 10.1109/ICICDT.2009.5166287

M3 - Conference contribution

AN - SCOPUS:77950312975

SN - 9781424429332

T3 - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

SP - 165

EP - 168

BT - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Y2 - 18 May 2009 through 20 May 2009

ER -

Song SC, Abu-Rahma M, Han BM, Ge L, Yoon SS, Wang J et al. Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 165-168. 5166287. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166287

Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

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