Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

S. C. Song, M. Abu-Rahma, B. M. Han, L. Ge, S. S. Yoon, J. Wang, W. Yang, D. Liu, Chen-Ming Hu, G. Yeap

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1μm2 below 32nm node.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages165-168
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States
Duration: 18 May 200920 May 2009

Publication series

Name2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
CountryUnited States
CityAustin, TX
Period18/05/0920/05/09

Keywords

  • 22nm
  • 32nm
  • Bitcell
  • FinFet
  • Icell
  • MuGFET
  • SNM
  • SRAM
  • Vccmin

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    Song, S. C., Abu-Rahma, M., Han, B. M., Ge, L., Yoon, S. S., Wang, J., Yang, W., Liu, D., Hu, C-M., & Yeap, G. (2009). Systematic approach of FinFET based SRAM bitcell design for 32nm node and below. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 165-168). [5166287] (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166287