TY - GEN
T1 - System-level verification on high-level synthesis of dataflow graph
AU - Chiang, Tsung Hsi
AU - Dung, Lan-Rong
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This paper presents a system-level verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.
AB - This paper presents a system-level verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.
UR - http://www.scopus.com/inward/record.url?scp=34547358209&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2006.1692708
DO - 10.1109/ISCAS.2006.1692708
M3 - Conference contribution
AN - SCOPUS:34547358209
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 807
EP - 810
BT - ISCAS 2006
Y2 - 21 May 2006 through 24 May 2006
ER -