System-level ESD protection design with on-chip transient detection circuit

Cheng Cheng Yen*, Ming-Dou Ker, Pi Chia Shih

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new on-chip transient detection circuit for systemlevel electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit has been analyzed to fix the system-level ESD issues. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages616-619
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period10/12/0613/12/06

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