Synthesizable injection-locked phase-locked loop with multiphase interlocking digitally controlled oscillator arrays

Yu Cheng Su, Kang Yu Chang, Yu Tung Chin, Chia Wen Chang, Shyh Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A synthesizable injection-locked phase-locked loop with multiphase interlocking digitally controlled oscillator arrays (SILPLL-IDCOS) is proposed. By doing interlocking of two digitally controlled oscillators (DCOs), the number of phase provided can be double and the oscillation frequency can be as fast as the original DCO. Moreover, it also adopts frequency tracking loop to isolate the injection path from the traditional PLL path in the ILPLL, so the race condition in the traditional ILPLL can be resolved. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. In the proposed synthesizable ILPLL, all logic cells and circuit components are using standard cell provided by foundry and our group. The total area of the synthesizable ILPLL core is only 0.01876 mm2 and provides 8 phase output. The post-layout simulated RMS jitter from a 5.024 GHz output frequency is 0.048 %UI. The total measured power consumption is 10.97 mW at 5.024 GHz output frequency and 78.5 MHz reference clock.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
EditorsFan Ye, Ting-Ao Tang
PublisherIEEE Computer Society
ISBN (Electronic)9781728107356
DOIs
StatePublished - Oct 2019
Event13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China
Duration: 29 Oct 20191 Nov 2019

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference13th IEEE International Conference on ASIC, ASICON 2019
CountryChina
CityChongqing
Period29/10/191/11/19

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  • Cite this

    Su, Y. C., Chang, K. Y., Chin, Y. T., Chang, C. W., & Jou, S. J. (2019). Synthesizable injection-locked phase-locked loop with multiphase interlocking digitally controlled oscillator arrays. In F. Ye, & T-A. Tang (Eds.), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019 [8983440] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON47005.2019.8983440