Surface treatment and electrical properties of directly wafer-bonded InP epilayer on GaAs substrate

Ray-Hua Horng*, W. C. Peng, D. S. Wuu, W. J. Ho, Y. S. Huang

*Corresponding author for this work

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

We have investigated the surface morphology and electrical properties of directly wafer-bonded GaAs and InP by surface treatment and fusion annealed temperatures. The surface morphologies of bond samples with and without pattern under uniaxial pressure with thermal treatment in N2 ambient were compared. It was found that the peeling, bubbles and cracks have almost completely eliminated and high quality fusion surface area of 2 cm × 2 cm can be obtained using the pattern with 3000 μm pitch and 10 μm width channel. Bonded interfaces were also characterized by transmission electron microscopy and revealed that neither threading dislocation nor stacking fault. The current-voltage characteristics have also been demonstrated to be results from different wafer cleaning processes and bonding at various temperatures. Using the H2SO4:H2O2:H2O and dilute HF etching solution, the free barrier interface of n-InP (2 × 1019 cm-3) bonded to n-GaAs (1 × 1018 cm-3) at 550 °C can be obtained.

Original languageEnglish
Pages (from-to)1103-1108
Number of pages6
JournalSolid-State Electronics
Volume46
Issue number8
DOIs
StatePublished - 1 Aug 2002

Keywords

  • Directly wafer bonded
  • Free barrier interface
  • Surface treatment

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