TY - JOUR
T1 - Surface potential mapping of p +/n-well junction by secondary electron potential contrast with in situ nano-probe biasing
AU - Lee, Jeng Han
AU - Liu, Po-Tsun
PY - 2012/7
Y1 - 2012/7
N2 - This article investigates the surface potential distribution of a biased p +/n-well diode using secondary electron potential contrast (SEPC) with an in situ nano-probe trigger. The SEPC image is digitized and quantified for the conversion of the image contrast to the voltage scale, allowing for the identification of the depletion region and the electrical junction. The overlap length between the poly silicon gate and the p + region is also depicted by two-dimensional (2-D) imaging. This study demonstrates that the proposed in situ nano-probe system is highly effective for surface potential mapping.
AB - This article investigates the surface potential distribution of a biased p +/n-well diode using secondary electron potential contrast (SEPC) with an in situ nano-probe trigger. The SEPC image is digitized and quantified for the conversion of the image contrast to the voltage scale, allowing for the identification of the depletion region and the electrical junction. The overlap length between the poly silicon gate and the p + region is also depicted by two-dimensional (2-D) imaging. This study demonstrates that the proposed in situ nano-probe system is highly effective for surface potential mapping.
KW - Nano-probe
KW - Scanning electron microscope (SEM)
KW - Secondary electron potential contrast (SEPC)
UR - http://www.scopus.com/inward/record.url?scp=84862786519&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2012.01.008
DO - 10.1016/j.mee.2012.01.008
M3 - Article
AN - SCOPUS:84862786519
VL - 95
SP - 5
EP - 9
JO - Microelectronic Engineering
JF - Microelectronic Engineering
SN - 0167-9317
ER -