Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

C. L. Yang*, C. H. Tsai, C. I. Li, C. Y. Tzeng, G. P. Lin, W. J. Chen, Y. L. Chin, C. I. Liao, M. Chan, J. Y. Wu, E. R. Hsieh, B. N. Guo, S. Lu, B. Colombeau, Steve S. Chung, I. C. Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.

Original languageEnglish
Article number6289339
Pages (from-to)1444-1446
Number of pages3
JournalIEEE Electron Device Letters
Volume33
Issue number10
DOIs
StatePublished - 1 Jan 2012

Keywords

  • Cryogenic implant
  • ion implantation
  • logic device
  • novel process technology
  • random dopant fluctuation

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    Yang, C. L., Tsai, C. H., Li, C. I., Tzeng, C. Y., Lin, G. P., Chen, W. J., Chin, Y. L., Liao, C. I., Chan, M., Wu, J. Y., Hsieh, E. R., Guo, B. N., Lu, S., Colombeau, B., Chung, S. S., & Chen, I. C. (2012). Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications. IEEE Electron Device Letters, 33(10), 1444-1446. [6289339]. https://doi.org/10.1109/LED.2012.2209395