Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

Jun Kai Zhao, Yi Wei Chiu, Shyh Jye Jou, Yuan Hua Chu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.

Original languageEnglish
Title of host publicationISOCC 2014 - International SoC Design Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages114-115
Number of pages2
ISBN (Electronic)9781479951260
DOIs
StatePublished - 16 Apr 2015
Event11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of
Duration: 3 Nov 20146 Nov 2014

Publication series

NameISOCC 2014 - International SoC Design Conference

Conference

Conference11th International SoC Design Conference, ISOCC 2014
CountryKorea, Republic of
CityJeju
Period3/11/146/11/14

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