This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.
- High-κ gate dielectric
- temperature dependence