Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric

Hei Wong*, B. L. Yang, K. Kakushima, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.

Original languageEnglish
Article number5898389
Pages (from-to)1002-1004
Number of pages3
JournalIEEE Electron Device Letters
Issue number8
StatePublished - Aug 2011


  • High-κ gate dielectric
  • LaO
  • MOS
  • temperature dependence

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