Submicrometer-Channel CMOS for Low-Temperature Operation

Jack Yuan Chen Sun, Yuan Taur, Robert H. Dennard, Stephen P. Klepner

Research output: Contribution to journalArticlepeer-review

92 Scopus citations

Abstract

A 0.5-μm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.

Original languageEnglish
Pages (from-to)19-27
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume34
Issue number1
DOIs
StatePublished - Jan 1987

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