Sub-sampling charge pump and random pulsewidth matching technique for frequency synthesizer

Te Wen Liao, Jun Ren Su, Chung-Chih Hung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of-114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below-74 dBc.

Original languageEnglish
Title of host publication2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
Pages1035-1038
Number of pages4
DOIs
StatePublished - 1 Dec 2013
Event2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH, United States
Duration: 4 Aug 20137 Aug 2013

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
CountryUnited States
CityColumbus, OH
Period4/08/137/08/13

Keywords

  • low spur
  • PLL
  • Synthesizer

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  • Cite this

    Liao, T. W., Su, J. R., & Hung, C-C. (2013). Sub-sampling charge pump and random pulsewidth matching technique for frequency synthesizer. In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 (pp. 1035-1038). [6674829] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2013.6674829