Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB

Zuow Zun Chen; Yen Hsiang Wang; Jaewook Shin; Yan Zhao; Seyed Arash Mirhaj; Yen-Cheng Kuan; Huan Neng Chen; Chewn Pu Jou; Ming Hsien Tsai; Fu Lung Hsueh; Mau-Chung Chang

doi:10.1109/ISSCC.2015.7063029

Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB

Zuow Zun Chen, Yen Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan Neng Chen, Chewn Pu Jou, Ming Hsien Tsai, Fu Lung Hsueh, Mau-Chung Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

34 Scopus citations

Abstract

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

Original language	English
Title of host publication	2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	268-269
Number of pages	2
ISBN (Electronic)	9781479962235
DOIs	https://doi.org/10.1109/ISSCC.2015.7063029
State	Published - 17 Mar 2015
Event	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States Duration: 22 Feb 2015 → 26 Feb 2015

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	58
ISSN (Print)	0193-6530

Conference

Conference	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Country	United States
City	San Francisco
Period	22/02/15 → 26/02/15

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10.1109/ISSCC.2015.7063029

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Chen, Z. Z., Wang, Y. H., Shin, J., Zhao, Y., Mirhaj, S. A., Kuan, Y-C., Chen, H. N., Jou, C. P., Tsai, M. H., Hsueh, F. L., & Chang, M-C. (2015). Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 268-269). [7063029] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7063029

Chen, Zuow Zun ; Wang, Yen Hsiang ; Shin, Jaewook ; Zhao, Yan ; Mirhaj, Seyed Arash ; Kuan, Yen-Cheng ; Chen, Huan Neng ; Jou, Chewn Pu ; Tsai, Ming Hsien ; Hsueh, Fu Lung ; Chang, Mau-Chung. / Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 268-269 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB",

abstract = "The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.",

author = "Chen, {Zuow Zun} and Wang, {Yen Hsiang} and Jaewook Shin and Yan Zhao and Mirhaj, {Seyed Arash} and Yen-Cheng Kuan and Chen, {Huan Neng} and Jou, {Chewn Pu} and Tsai, {Ming Hsien} and Hsueh, {Fu Lung} and Mau-Chung Chang",

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Chen, ZZ, Wang, YH, Shin, J, Zhao, Y, Mirhaj, SA, Kuan, Y-C, Chen, HN, Jou, CP, Tsai, MH, Hsueh, FL & Chang, M-C 2015, Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. in 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers., 7063029, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 58, Institute of Electrical and Electronics Engineers Inc., pp. 268-269, 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, San Francisco, United States, 22/02/15. https://doi.org/10.1109/ISSCC.2015.7063029

Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. / Chen, Zuow Zun; Wang, Yen Hsiang; Shin, Jaewook; Zhao, Yan; Mirhaj, Seyed Arash; Kuan, Yen-Cheng; Chen, Huan Neng; Jou, Chewn Pu; Tsai, Ming Hsien; Hsueh, Fu Lung; Chang, Mau-Chung.

2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 268-269 7063029 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB

AU - Chen, Zuow Zun

AU - Wang, Yen Hsiang

AU - Shin, Jaewook

AU - Zhao, Yan

AU - Mirhaj, Seyed Arash

AU - Kuan, Yen-Cheng

AU - Chen, Huan Neng

AU - Jou, Chewn Pu

AU - Tsai, Ming Hsien

AU - Hsueh, Fu Lung

AU - Chang, Mau-Chung

PY - 2015/3/17

Y1 - 2015/3/17

N2 - The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

AB - The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

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T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 268

EP - 269

BT - 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 February 2015 through 26 February 2015

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Chen ZZ, Wang YH, Shin J, Zhao Y, Mirhaj SA, Kuan Y-C et al. Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 268-269. 7063029. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2015.7063029