Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB

Zuow Zun Chen, Yen Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan Neng Chen, Chewn Pu Jou, Ming Hsien Tsai, Fu Lung Hsueh, Mau-Chung Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

34 Scopus citations

Abstract

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

Original languageEnglish
Title of host publication2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages268-269
Number of pages2
ISBN (Electronic)9781479962235
DOIs
StatePublished - 17 Mar 2015
Event2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States
Duration: 22 Feb 201526 Feb 2015

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume58
ISSN (Print)0193-6530

Conference

Conference2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
CountryUnited States
CitySan Francisco
Period22/02/1526/02/15

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