Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, Hung-Ming Chen, B. D. Rong, K. Itoh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages227-230
Number of pages4
ISBN (Electronic)9781728151069
DOIs
StatePublished - Nov 2019
Event15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China
Duration: 4 Nov 20196 Nov 2019

Publication series

NameProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
CountryChina
CityMacao
Period4/11/196/11/19

Keywords

  • 5T bit (memory) cell
  • gate-boosting driver
  • low-power array
  • Sub-0.5 V SRAM

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