Sub-nanometer high-k gate stack scaling using the HF-last/NH3 anneal interface

Jeff J. Peterson*, Joel Barnett, Chadwin D. Young, Tuo-Hung Hou, Jim Gutt, Sundar Gopalan, Choong Ho Lee, Hong Jyb Li, Naim Moumen, Nirmal Chaudhary, Byoung Hun Lee, Gennadi Bersuker, Peter M. Zeitzoff, George A. Brown, Pat Lysaght, Mark Gardner, Robert W. Murto, Howard R. Huff

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review


The scaling of high-k gate stacks using an HF-last/NH3 anneal bottom interface was evaluated for EOT, Nit, and mobility effects on HfC2polysilicon and HfO2/metal gate transistors. TEM analysis of HF-last/NH3 bottom interface layers was also done, showing HF-Iast/NH3 and O3 bottom interface layer thickness to be identical within the resolution of the measurement. Electrical characterization showed that use of HF-last/NH3 anneal bottom interface reduces the EOT of high-k/polysilicon gate devices by 0.3 nm and high-k/metal gate devices by about 0.15-0.2 nm with respect to the corresponding ozonated (O3) interface sample. Charge pumping on the HF-last/NH3 anneal bottom interface indicated Nit density of ∼5×1010 cm-2, slightly greater than the O3 interface control, with mobilities nearly equivalent to those in corresponding O3 interface devices. These data show NH3 bottom interface chemistry to be highly effective in scaling the EOT of HfO 2/polysilicon and HfO2/metal gate stacks while giving nearly equivalent electrical characteristics in transistors fabricated using this method.

Original languageEnglish
Number of pages7
StatePublished - 1 Dec 2003
EventCleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium - Orlando, FL., United States
Duration: 12 Oct 200317 Oct 2003


ConferenceCleaning Technology in Semiconductor Device Manufacturing VIII - Proceedings of the International Symposium
CountryUnited States
CityOrlando, FL.

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