Sub-60nm Si tunnel field effect transistors with I on >100 μA/μm

Wei Yip Loh*, Kanghoon Jeon, Chang Yong Kang, Jungwoo Oh, Pratik Patel, Casey Smith, Joel Barnett, Chanro Park, Tsu Jae King Liu, Hsing Huang Tseng, Prashant Majhi, Raj Jammy, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

Si-tunneling field effect transistors (TFETs) with a record I o n >100 μA/μm and high I o n/I o f f ratio (> 10 5 ) at V d s=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFET s have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential resistance and temperature dependencies consistent with band-to-band tunneling and current characteristics in excellent agreement with 2D TCAD simulations.

Original languageEnglish
Title of host publication2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
Pages162-165
Number of pages4
DOIs
StatePublished - 15 Dec 2010
Event2010 European Solid State Device Research Conference, ESSDERC 2010 - Sevilla, Spain
Duration: 14 Sep 201016 Sep 2010

Publication series

Name2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Conference

Conference2010 European Solid State Device Research Conference, ESSDERC 2010
CountrySpain
CitySevilla
Period14/09/1016/09/10

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    Loh, W. Y., Jeon, K., Kang, C. Y., Oh, J., Patel, P., Smith, C., Barnett, J., Park, C., Liu, T. J. K., Tseng, H. H., Majhi, P., Jammy, R., & Hu, C-M. (2010). Sub-60nm Si tunnel field effect transistors with I on >100 μA/μm. In 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010 (pp. 162-165). [5618418] (2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010). https://doi.org/10.1109/ESSDERC.2010.5618418