Sub-60mV-swing negative-capacitance FinFET without hysteresis

Kai Shin Li, Pin Guang Chen, Tung Yan Lai, Chang Hsien Lin, Cheng Chih Cheng, Chun Chi Chen, Yun Jie Wei, Yun Fang Hou, Ming Han Liao, Min Hung Lee, Min Cheng Chen, Jia Min Sheih, Wen Kuan Yeh, Fu Liang Yang, Sayeef Salahuddin, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

156 Scopus citations


In this work, we report the first Negative-Capacitance FinFET. ALD Hf 042 Zr 058 O 2 is added on top of the FinFET's gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). ION increased by >25% for the IOFF. For the first time, we demonstrate that raising HfZrO 2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.

Original languageEnglish
Title of host publication2015 IEEE International Electron Devices Meeting, IEDM 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467398930
StatePublished - 16 Feb 2015
Event61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States
Duration: 7 Dec 20159 Dec 2015

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918


Conference61st IEEE International Electron Devices Meeting, IEDM 2015
CountryUnited States

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