Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

Nick Lindert*, Leland Chang, Yang Kyu Choi, Erik H. Anderson, Wen Chin Lee, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

133 Scopus citations

Abstract

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. Drive current for typical devices is found to be above 500μA/μm (or 1mA/μm, depending on the definition of the width of the double-gate device) for Vg - Vt : Vd = 1 V. The electrical gate oxide thickness in these devices is 21A, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.

Original languageEnglish
Pages (from-to)487-489
Number of pages3
JournalIEEE Electron Device Letters
Volume22
Issue number10
DOIs
StatePublished - 1 Oct 2001

Keywords

  • Double-gate
  • Double-resist process
  • Fin
  • FinFET
  • MOSFET
  • Short-channel effects
  • SiGe gate

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    Lindert, N., Chang, L., Choi, Y. K., Anderson, E. H., Lee, W. C., King, T. J., Bokor, J., & Hu, C-M. (2001). Sub-60-nm quasi-planar FinFETs fabricated using a simplified process. IEEE Electron Device Letters, 22(10), 487-489. https://doi.org/10.1109/55.954920