Sub-50 nm P-channel FinFET

Xuejue Huang*, Wen Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

238 Scopus citations

Abstract

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raises S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I dsat of 820 μA/μm at V ds = V gs = 1.2 V and T ox = 2.5 nm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

Original languageEnglish
Pages (from-to)880-886
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume48
Issue number5
DOIs
StatePublished - 1 May 2001

Keywords

  • Double-gate MOSFETs
  • Fully depleted
  • MOS devices
  • Scaled CMOS
  • Short-channel effect
  • Silicon-germanium (SiGe)
  • SOI MOSFETs

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