Sub-50 NM gate length N-MOSFETS with 10 NM phosphorus source and drain unctions

Mizuki Ono*, Masanobu Saito, Takashi Youshitomi, Claudio Fiegna, Tatsuya Ohguro, Hiroshi Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

115 Scopus citations

Abstract

Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects - V shift and S-factor degradation - are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of V d less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Editors Anon
PublisherPubl by IEEE
Pages119-122
Number of pages4
ISBN (Print)0780314506
StatePublished - 1993
EventProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
Duration: 5 Dec 19938 Dec 1993

Publication series

NameTechnical Digest - International Electron Devices Meeting
ISSN (Print)0163-1918

Conference

ConferenceProceedings of the 1993 IEEE International Electron Devices Meeting
CityWashington, DC, USA
Period5/12/938/12/93

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