Sub 50-nm FinFET: PMOS

Xuejue Huang*, Wen Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

414 Scopus citations

Abstract

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an Idsat of 410 μA/μm (or 820 μA/μm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

Original languageEnglish
Pages (from-to)67-70
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1999
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 5 Dec 19998 Dec 1999

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