A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET . Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 2001|
|Event||IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States|
Duration: 2 Dec 2001 → 5 Dec 2001