Sub-20nm CMOS FinFET technologies

Yang Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang*, Daewon Ha, Erik Anderson, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

168 Scopus citations


A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET [1][2]. Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.

Original languageEnglish
Pages (from-to)421-424
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 2001
EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
Duration: 2 Dec 20015 Dec 2001

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