Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture

Toshihiko Iinuma, Nobuyuki Itoh, Hiroomi Nakajima, Kazumi Inou, Satoshi Matsuda, Chihiro Yoshino, Yoshiroh Tsuboi, Yasuhiro Katsumata, Hiroshi Iwai

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing fT values. In this paper, we demonstrate a device with sub-20 ps tpd values even at fT = 23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce CCB, 2) a low-concentration collector design to reduce CCB, 3) NiSi-salicided base and emitter electrodes to reduce RB, and 4) a shallow base formed by double diffusion technology for relatively high fT with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V.

Original languageEnglish
Pages (from-to)399-405
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number3
StatePublished - Mar 1995

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