Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD

Pin Su, S. K.H. Fung, Weidong Liu, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

In this, work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit, designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.

Original languageEnglish
Title of host publicationProceedings of the 2002 3rd International Symposium on Quality Electronic Design, ISQED 2002
PublisherIEEE Computer Society
Pages487-491
Number of pages5
ISBN (Electronic)0769515614
DOIs
StatePublished - 1 Jan 2002
Event3rd International Symposium on Quality Electronic Design, ISQED 2002 - San Jose, United States
Duration: 18 Mar 200221 Mar 2002

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2002-January
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference3rd International Symposium on Quality Electronic Design, ISQED 2002
CountryUnited States
CitySan Jose
Period18/03/0221/03/02

Keywords

  • Bridge circuits
  • Circuit simulation
  • Computational modeling
  • Delay
  • History
  • Hysteresis
  • Inverters
  • SPICE
  • Semiconductor device modeling
  • Tunneling

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