Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin, Ming-Dou Ker, Pin Hsin Chang, Wen Tai Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

Original languageEnglish
Title of host publication2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467393621
DOIs
StatePublished - 22 Mar 2016
Event10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 - Anchorage, United States
Duration: 12 Sep 201516 Sep 2015

Publication series

Name2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

Conference

Conference10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
CountryUnited States
CityAnchorage
Period12/09/1516/09/15

Keywords

  • CMOS
  • electrostatic discharge (ESD)
  • high-k metal-gate (HKMG)
  • silicon-controlled rectifier (SCR)

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    Lin, C. Y., Ker, M-D., Chang, P. H., & Wang, W. T. (2016). Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. In 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 [7439250] (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2015.7439250