Study on random telegraph noise of gate-ail-around poly-Si junctionless nanowire transistors

Chen Chen Yang, Kang Ping Peng, Yung Chen Chen, Horng-Chih Lin*, Pei-Wen Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this work we study the random telegraph noise (RTN) characteristics of short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors. The test devices were fabricated with I-line-based lithography in combination with novel spacer-etching techniques for aggressively shrinking the channel dimension. Based on the tiny nanowire channel and short-channel length, we are able to detect clear RTN signals as the gate voltage is sufficiently large. Location of the trap responsible for the RTN is estimated to be 1.13 nm within the gate oxide away from the oxide/channel interface.

Original languageEnglish
Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages45-46
Number of pages2
ISBN (Electronic)9784863486478
DOIs
StatePublished - 29 Dec 2017
Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
Duration: 4 Jun 20175 Jun 2017

Publication series

Name2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume2017-January

Conference

Conference22nd Silicon Nanoelectronics Workshop, SNW 2017
CountryJapan
CityKyoto
Period4/06/175/06/17

Fingerprint Dive into the research topics of 'Study on random telegraph noise of gate-ail-around poly-Si junctionless nanowire transistors'. Together they form a unique fingerprint.

Cite this