The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30- V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.
|Title of host publication||Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018|
|State||Published - 25 Oct 2018|
|Event||40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 - Reno, United States|
Duration: 23 Sep 2018 → 28 Sep 2018
|Name||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|Conference||40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018|
|Period||23/09/18 → 28/09/18|