Study on latchup path between HV-LDMOS and LVCMOS in a 0.16-μm 30-V/1.8-V BCD technology

Chia Tsen Dai, Ming-Dou Ker, Yeh Ning Jou, Shao Chang Huang, Geeng Lih Lin, Jian Hsing Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30- V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018
PublisherESD Association
ISBN (Electronic)1585373028
DOIs
StatePublished - 25 Oct 2018
Event40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 - Reno, United States
Duration: 23 Sep 201828 Sep 2018

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2018-September
ISSN (Print)0739-5159

Conference

Conference40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018
CountryUnited States
CityReno
Period23/09/1828/09/18

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