Study of trap generation in the Sc2O3/La 2O3/SiOx gate dielectric stack by scanning tunneling microscopy

Yi Ching Ong*, Diing Shenp Ang, Sean Joseph O'Shea, Kin Leong Pey, Kuniyuki Kakushima, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalReview articlepeer-review


Scanning tunneling microscopy is used to study trap evolution in the Sc2O3/La2O3/SiOx gates tack. Current-voltage characteristics extracted from leakage sites exhibit stress-induced-leakage-current (SILC) or barrier-height-lowering (BHL) behavior. The high-κ layer is observed to have larger intrinsic trap generation rate, compared to the SiOx layer, due to a higher surface plasmon generated hot-hole current at the tip/high-κ interface. In the presence of electronic traps: (i) SILC traps near the cathode inhibit trap generation in the layer near the anode due to inelastic-trap-assisted-tunneling mechanism; (ii) SILC traps near the cathode may evolve into BHL as lattice displacement due to electron charging during the inelastic-trap-assisted tunneling process may accelerate the wear-out of the neighboring region; and (iii) traps with BHL characteristics in the high-κ may accelerate the breakdown of the Interfacial layer (IL) due to enhanced electric field in the IL. An electrical stress induced trap evolution model in the gate stack is proposed.

Original languageEnglish
Pages (from-to)427-436
Number of pages10
JournalJournal of the Vacuum Society of Japan
Issue number7-8
StatePublished - 2011

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