Study of self-align doped channel structure for low power and low 1/f noise operation

Takashi Yoshitomi*, Hideki Kimijima, Shinnichiro Ishizuka, Yasunori Miyahara, Tatsuya Ohguro, Eiji Morifuji, Toyota Morimoto, Hisayo Sasaki Momose, Yasuhiro Katsumata, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

Self-align doped channel (SADC) which can minimize the 1/f noise and junction capacitance is studied. Several severe expected problems such as the controllability of the diffusion and TDDB of the gate oxide are overcome to be seriously considered for the products. In addition, this structure is attractive for small geometry high performance deice with low capacitance and low 1/f noise.

Original languageEnglish
Pages (from-to)98-99
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1998
EventProceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 9 Jun 199811 Jun 1998

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