Study of low-temperature and post-stress hysteresis in high-k gate dielectrics

You Lin Wu*, Shi Tin Lin, Chang Cheng Yang, Chien Hung Wu, Albert Chin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this work, we present the comparison of hysteresis behaviors of HfAlON and HfSiON high-k dielectrics at low-temperature and subjected to constant voltage stress (CVS). The VFB instability in the HfAlON and HfSiON gate dielectric were deeply studied. A model is proposed to explain the V FB Shift and hysteresis direction in thus two samples. We also treat the CVS voltage and CVS time dependence of hysteresis and VFB Shift. The decreasing hysteresis with temperature is ascribed to traps generation/recombination rate reduction at low temperature.

Original languageEnglish
Title of host publicationIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages653-656
Number of pages4
DOIs
StatePublished - 1 Dec 2007
EventIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan
Duration: 20 Dec 200722 Dec 2007

Publication series

NameIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

ConferenceIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
CountryTaiwan
CityTainan
Period20/12/0722/12/07

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