Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R ON C ESD, I CP/C ESD, V HBM/C ESD, and I CP/A Layout) of ESD protection diodes with new proposed layout styles can be successfully improved.

Original languageEnglish
Pages (from-to)1020-1030
Number of pages11
JournalMicroelectronics Reliability
Volume52
Issue number6
DOIs
StatePublished - 1 Jun 2012

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