Study of discrete voids formation in flip-chip solder joints due to electromigration using in-situ 3D laminography and finite-element modeling

Yuan Wei Chang*, Yin Cheng, Feng Xu, Lukas Helfen, Tian Tian, Marco Di Michiel, Chih Chen, King-Ning Tu, Tilo Baumbach

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Nowadays, the microelectronics industry broadly uses the flipchip technology to enhance the packaging density. However, the small size and the unique geometry of the flip-chip solder joints induce the electromigration (EM) reliability issue. In this study, a Pb-free solder joints (SAC1205) was EM tested by a current of 7.5×103 A/cm2. During the tests, a three-dimensional (3D) X-ray laminography method was applied to in-situ observe the microstructure evolution. The laminography method allows for the non-destructive observation and provides the quantitative analysis among three dimensions. After EM testing for 650 hr, a new EM failure mechanism was found rather than the well-known models, the pancake void propagation and the under-bump-metallization dissolution. According to the laminography images at different testing stages, many voids simultaneously formed and grew during the entire procedure of testing. Most of them distributed in the current crowding region, but a few also located in the low-current-density region. As the testing time increased, voids grew bigger, coalesced with each other, and finally became large voids which occupied the interface and caused EM failure. The finite-element (FE) method was also applied to analyze the interplay between the microstructure evolution and current density redistribution. A series of 3D FE models were built based on the laminography images at different testing stages. The current density distribution from the FE analysis indicates that the multiple voids formation does not affect the global current density distribution until the voids merged together and became very large voids in the late stage of EM testing. The relieving of the global current crowding in the pancake void model was not found in this new EM failure mechanism. It was the local current crowding found in the new model that responsible for the EM retardation.

Original languageEnglish
Title of host publicationProceedings of the 2016 IEEE 18th Electronics Packaging Technology Conference, EPTC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages141-146
Number of pages6
ISBN (Electronic)9781509043682
DOIs
StatePublished - 21 Feb 2017
Event18th IEEE Electronics Packaging Technology Conference, EPTC 2016 - Singapore, Singapore
Duration: 30 Nov 20163 Dec 2016

Publication series

NameProceedings of the 2016 IEEE 18th Electronics Packaging Technology Conference, EPTC 2016

Conference

Conference18th IEEE Electronics Packaging Technology Conference, EPTC 2016
CountrySingapore
CitySingapore
Period30/11/163/12/16

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