The contact resistance between TiSi//2 and shallow n** plus /p** plus source-drains in CMOS is studied for a variety of junction depths and silicide thicknesses. The contact contribution to the total device series resistance can be significant if excessive silicon and dopants are consumed during silicide formation. Low contact resistances are obtained for 0. 15- mu m n** plus and 0. 20- mu m p** plus junctions when the titanium thickness is reduced to keep a high doping concentration at the TiSi//2/Si interface. Alternatively, a nonstandard process can be employed to implant additional dopants into the titanium. A thin layer of dopants then out-diffuses into the silicon after the silicide reaction and anneal to help reduce contact resistance and leakage currents. The latter technique is more extendable to CMOS devices which require thicker titanium films and/or shallower junctions.