P+-poly gate capacitors as well as dual (n+ and p+)-poly CMOS devices with oxide thickness ranging from 4 to 13 nm were fabricated to study temperature and ambient effects on boron penetration, threshold voltage control, and the compatibility of p+-poly with passivation, reflow and other CMOS FEOL/BEOL processes. It was found that boron penetration introduces VT shift and degrades VT control. The thermal cycle, poly gate thickness, and boron dose should be optimized to meet the requirement of p+-poly work function without causing boron penetration. Care must be taken to minimize hydrogen or moisture in the annealing ambient after boron is implanted into the poly gate. RTA (rapid thermal anneal) allows the highest temperature for p+-poly processing without boron penetration. Conventional passivation/steam reflow processes may not be compatible with p+-poly depending on the gate oxide thickness and reflow temperature. Finally, a degenerate p+-poly gate is demonstrated on 4-nm SiO2 without boron penetration, showing the extendability of the dual (n+ and p+)-poly process to future CMOS ULSI of sub-0.25μm channel lengths.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1989|
|Event||Ninth Symposium on VLSI Technology 1989 - Digest of Technical Papers - Kyoto, Jpn|
Duration: 22 May 1989 → 25 May 1989