Study and Verification on the Latch-Up Path between I/O pMOS and N-Type Decoupling Capacitors in 0.18-\mu m CMOS Technology

Chun Cheng Chen, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-Type decoupling capacitors may be accidentally triggered on. In this paper, the non-Typical latch-up path between I/O pMOS and n-Type decoupling capacitors was investigated in 0.18-{\mu }\text{m} 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-Type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path.

Original languageEnglish
Article number8714051
Pages (from-to)445-451
Number of pages7
JournalIEEE Transactions on Device and Materials Reliability
Volume19
Issue number2
DOIs
StatePublished - 1 Jun 2019

Keywords

  • Latch-up
  • decoupling capacitor
  • silicon-controlled rectifier (SCR)
  • varactor

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