Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

C. T. Ko*, Z. C. Hsiao, Y. J. Chang, P. S. Chen, J. H. Huang, H. C. Fu, Y. J. Huang, C. W. Chiang, C. K. Lee, H. H. Chang, W. L. Tsai, Y. H. Chen, W. C. Lo, Kuan-Neng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.

Original languageEnglish
Title of host publication2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012
Pages1-7
Number of pages7
DOIs
StatePublished - 4 Oct 2012
Event2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012 - San Diego, CA, United States
Duration: 29 May 20121 Jun 2012

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Conference

Conference2012 IEEE 62nd Electronic Components and Technology Conference, ECTC 2012
CountryUnited States
CitySan Diego, CA
Period29/05/121/06/12

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