Structural and electrical properties of high-k HoTiO3 gate dielectrics

Tung Ming Pan*, Li Chen Yen, Chia Wei Hu, Tien-Sheng Chao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

We developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800°C exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition.

Original languageEnglish
Title of host publicationAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages241-245
Number of pages5
Edition1
DOIs
StatePublished - 30 Dec 2010
EventAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, Canada
Duration: 26 Apr 201027 Apr 2010

Publication series

NameECS Transactions
Number1
Volume28
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting
CountryCanada
CityVancouver, BC
Period26/04/1027/04/10

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