Stress migration (SM) and electromigration (EM) were widely used to study the performance of interconnection process of metal/via formation in copper dual damascene of wafers. Necking and voids at the via bottom were important in causing failures in tests of stress migration and electromigration. In this report, the contamination of the bottom of via, which results in poor step coverage, the adhesion of seed layers, and poor copper grain formation are identified to be the underlying causes of the necking and void formation after the first EM and SM tests are performed. The contamination of the via formation processes included via etching, trench etching, and barrier/seed layer depositions. A well-shaped via profile can be optimized using three methods, the first involves Cu/SiN interface stress, the second involves Cu grain growth, and the third involves post via etching clean study. Eliminating the contamination of the via bottom and optimizing step coverage and adhesion of the barrier seed layers improve the EM and SM performance from time-to-fail = 13 to 59 s, in the copper-related processes for fabricating 300 mm wafers using technology that is beyond 0.13 μm technology.