An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 1 Oct 2004|
|Event||2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States|
Duration: 15 Jun 2004 → 17 Jun 2004