Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

Fu Liang Yang*, Hou Yu Chen, Chien Chao Huang, Chun Hu Ge, Ke Wei Su, Cheng Chuan Huang, Chang Yun Chang, Da Wen Lin, Chung Cheng Wu, Jaw Kang Ho, Wen Chin Lee, Yee Chia Yeo, Carlos H. Diaz, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations


A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Original languageEnglish
Pages (from-to)137-138
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1 Oct 2003
Event2003 Symposium on VLSI Technology - Kyoto, Japan
Duration: 10 Jun 200312 Jun 2003

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