Strained CMOS devices with shallow-trench-isolation stress buffer layers

Yi-Ming Li*, Hung Ming Chen, Shao Ming Yu, Jiunn Ren Hwang, Fu Liang Yang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Scopus citations


In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.

Original languageEnglish
Article number4457870
Pages (from-to)1085-1089
Number of pages5
JournalIEEE Transactions on Electron Devices
Issue number4
StatePublished - Apr 2008


  • Channel surface buffer layer
  • Fabrication
  • Measurement
  • Mobility
  • MOS devices
  • Shallow-trench isolation (STI)
  • Sidewall stress buffer layer
  • Simulation
  • Transport characteristics

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