Stochastic STT-MRAM Spiking Neuron Circuit

Fu Xiang Liang, Paritosh Sahu, Ming Hung Wu, Jeng Hua Wei, Shyh Shyuan Sheu, Tuo Hung Hou*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages151-152
Number of pages2
ISBN (Electronic)9781728142326
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

Fingerprint Dive into the research topics of 'Stochastic STT-MRAM Spiking Neuron Circuit'. Together they form a unique fingerprint.

Cite this