We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.