Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model

Che Hua Shih*, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

Verifying if an integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite state machine (NEFSM), and then propose an automatic stimulus generation approach based on the NEFSM. This approach is capable of providing numerous biasing options. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.

Original languageEnglish
Title of host publicationProceedings - Tenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05
Pages87-93
Number of pages7
DOIs
StatePublished - 1 Dec 2005
EventTenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05 - Napa Valley, CA, United States
Duration: 30 Nov 20052 Dec 2005

Publication series

NameProceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
Volume2005
ISSN (Print)1552-6674

Conference

ConferenceTenth Annual IEEE International High Level Design Validation and Test Workshop, HLDVT'05
CountryUnited States
CityNapa Valley, CA
Period30/11/052/12/05

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