Statistical techniques for predicting system-level failure using stress-test data

Harry H. Chen, Shih Hua Kuo, Jonathan Tung, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's 'analog' failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
PublisherIEEE Computer Society
ISBN (Electronic)9781479975976
DOIs
StatePublished - 1 Jun 2015
Event2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
Duration: 27 Apr 201529 Apr 2015

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2015-January

Conference

Conference2015 33rd IEEE VLSI Test Symposium, VTS 2015
CountryUnited States
CityNapa
Period27/04/1529/04/15

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  • Cite this

    Chen, H. H., Kuo, S. H., Tung, J., & Chao, C-T. (2015). Statistical techniques for predicting system-level failure using stress-test data. In Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015 [7116260] (Proceedings of the IEEE VLSI Test Symposium; Vol. 2015-January). IEEE Computer Society. https://doi.org/10.1109/VTS.2015.7116260