Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators

Szu Pang Mu, Chia-Tso Chao, Shi Hao Chen, Yi Ming Wang

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip's maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

Original languageEnglish
Article number7294704
Pages (from-to)1675-1687
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number5
DOIs
StatePublished - 1 May 2016

Keywords

  • Machine learning
  • rind oscillator
  • speed binning.

Fingerprint Dive into the research topics of 'Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators'. Together they form a unique fingerprint.

  • Cite this