Aggressive scaling of CMOS MOSFET gate lengths is halving minimum device channel lengths every 4 to 6 years. This brings an increase in deep submicron device performance sensitivity to manufacturing variations. Its impact on highly-integrated, system-on-a-chip designs needs assessment to ensure first-pass silicon and adequate yield. Standard simulations to assess these impacts are performed at SPICE simulation level and rely upon a multivariate statistical technique called principal component analysis. This method is popular because it reduces the large number of correlated SPICE model parameters characteristic of current deep-submicron models into few statistically independent factors which can then be generated by Monte Carlo simulation.
|Number of pages||2|
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 1 Jan 1998|
|Event||Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA|
Duration: 5 Feb 1998 → 7 Feb 1998