Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Cheng-Yun Hsueh, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-mu m CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.

Original languageEnglish
Pages (from-to)1461-1470
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume68
Issue number4
DOIs
StatePublished - Apr 2021

Keywords

  • Charged-device model (CDM)
  • cross-domainESD protection
  • electrostatic discharge (ESD) protection
  • multiple power domains
  • stacking metal-oxide-semiconductor (MOS) structure

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