Stack memory design for a low-cost instruction folding Java processor

Zi Gang Lin*, Han Wen Kuo, Zi Jing Guo, Chun-Jen Tsai

*Corresponding author for this work

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

In this paper, we propose the design of the stack memory for a low-cost Java processor that explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance Java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the Java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM; and is optimized for the Java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.

Original languageEnglish
Pages3226-3229
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

Keywords

  • embedded systems
  • instruction-level parallelism
  • Java processor
  • stack memory design

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  • Cite this

    Lin, Z. G., Kuo, H. W., Guo, Z. J., & Tsai, C-J. (2012). Stack memory design for a low-cost instruction folding Java processor. 3226-3229. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6272011