Stability/Performance Assessment of Monolithic 3D 6T/8T SRAM Cells Considering Transistor-Level Interlayer Coupling

Ming Long Fan, Vita Pi Ho Hu, Yin Nien Chen, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance.
Original languageEnglish
Title of host publicationProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
PublisherIEEE Computer Society
ISBN (Print)9781479922178
DOIs
StatePublished - 1 Jan 2014
Event2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

Conference

Conference2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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  • Cite this

    Fan, M. L., Hu, V. P. H., Chen, Y. N., Su, P., & Chuang, C. T. (2014). Stability/Performance Assessment of Monolithic 3D 6T/8T SRAM Cells Considering Transistor-Level Interlayer Coupling. In Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 [6839680] (Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-TSA.2014.6839680