SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Mukhopadhyay Saibal, Rao Rahul M., Jae-Joon Kim, Ching-Te Chuang

Research output: Contribution to journalArticle

51 Scopus citations


Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.
Original languageEnglish
Pages (from-to)24-32
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
StatePublished - Jan 2011


  • Capacitive coupling; SRAM; variation; write-ability

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