Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.
|Number of pages||9|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jan 2011|
- Capacitive coupling; SRAM; variation; write-ability
- ENHANCEMENT; DESIGN
Saibal, M., Rahul M., R., Kim, J-J., & Chuang, C-T. (2011). SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(1), 24-32. https://doi.org/10.1109/TVLSI.2009.2029114